Phase-locked loop with variable gain and bandwidth

ABSTRACT

A phase locked loop includes a voltage-controlled oscillator, and a phase and frequency detector for comprising an input signal pulse wave with a pulse wave from the voltage-controlled oscillator, and for providing a frequency control voltage to the voltage-controlled oscillator. When the pulses overlap, a pulse comparison circuit in the phase and frequency detector produces a frequency &#34;up&#34; signal or a frequency &#34;down&#34; signal proportional to the correction necessary. When the pulses do not overlap, the pulse comparison circuit produces a &#34;non-overlap&#34; signal which effects a rapid frequency correction by causing a current pump in the phase and frequency detector to increase its output to a fixed maximum value, and by causing a loop filter to increase its bandwidth to a fixed maximum value.

This invention relates to a phase locked loop useful, for example, in frequency synthesizers.

According to an example of the invention, a phase locked loop includes a phase and frequency detector for comparing input and oscillator pulses and for supplying a proportional correction voltage to the oscillator when the pulses overlap and for supplying a maximum correction voltage when the pulses do not overlap.

In the drawing:

FIG. 1 is a schematic diagram of a phase locked loop constructed according to the teachings of the invention;

FIG. 2 is a diagram describing the phase characteristics of the phase and frequency detector circuit included in FIG. 1;

FIG. 3 is a graph illustrating the frequency characteristics of the phase and frequency detector included in FIG. 1; and

FIGS. 4 and 5 are charts of voltage waveforms which will be referred to in describing the operation of the phase and frequency detector of FIG. 1.

Referring now in greater detail to FIG. 1, the phase locked loop shown includes a phase and frequency detector consisting of a pulse comparison circuit 10, a variable-gain current pump 12, and a variable-bandwidth loop filter 14. The phase and frequency detector has a first input at 16 for a pulse wave signal f₁ ' derived by a pulse shaper 18 from an input sine wave signal f₁, and has a second input at 20 for a pulse wave signal f₂ ' derived by a pulse shaper 22 from the sine wave output f₂ from a voltage-controlled oscillator 24. The pulses of pulse waves f₁ ' and f₂ ' may have equal widths, equal to 10 percent of the periods of the waves. The actual percentage figure adopted for the widths of the pulses determines the dividing point between the two modes of operation of the phase locked loop, as will be apparent as the description proceeds. The output frequency f₂ from the oscillator 24 is controlled by a control signal V₀ generated by the phase and frequency detector including the pulse comparison circuit 10, the variable-gain current pump 12 and the variable-bandwidth filter 14.

The pulse comparison circuit 10 includes first and second positive-edge-triggered Type D flip-flops F₁ and F₂ having trigger inputs C for input pulse wave f₁ ' and oscillator pulse wave f₂ ' respectively, Q₁ and Q₂ outputs, respectively and reset inputs R₁ and R₂. Flip-flops F₁ and F₂ may be Type SN7474 units manufactured by Texas Instruments. A "nand" gate 26 has inputs from the Q₁ and Q₂ outputs of the two flip-flops F₁ and F₂, and has an output connected to the reset inputs of the two flip-flops.

Third and fourth flip-flops F₃ and F₄ are set-reset flip-flops which are set and reset on receipt at S and R, respectively, of positive voltage level signals. The flip-flops F₃ and F₄ have set outputs at Q₃ and Q₄, respectively. The flip-flops F₃ and F₄ may be constructed by cross coupling two "nor" gates such as the gates Type SN5402 manufactured by Texas Instruments.

The first input terminal 16 of the pulse comparison circuit is connected to the trigger input C of flip-flop F₁ and the reset input R of flip-flop F₃. The Q₁ output of flip-flop F₁ is connected to the set input of flip-flop F₃ and to one input of an "up" gate G₁ having another input from the Q₃ output of flip-flop F₃. Corresponding mirror image connections are made between second input terminal 20, second flip-flop F₂, fourth flip-flop F₄ and a "down" gate G₂. Gates G₁ and G₂ are "nor" gates. A "non-overlap" gate G₃ is an "or" gate having inputs from the Q₃ and Q₄ outputs of flip-flops F₃ and F₄.

The "up" and "down" outputs from pulse comparison circuit 10 are applied to input transistors T₂ and T₄ of a variable-gain current pump 12 having a gain control transistor T₁. In the normal condition when the system is in phase and frequency lock, current pump transistor T₁ is on, and transistors T₂, T₃ and T₄ are off. An "up" pulse from gate G₁ renders transistor T₂ conductive and the current drawn therethrough from resistor R₁ ' causes transistor T₃ to conduct from source V to capacitor C₁ in the variable bandwidth filter 14. This increases the charge on the filter and increases the control voltage V₀. A "down" pulse from gate G₂ renders transistor T₄ conductive to draw charge from capacitor C₁ in filter 14 and cause a decrease in the charge on capacitor C₁ and in voltage V₀.

When the input pulses f₁ ' and f₂ ' overlap, the widths of the "up" and "down" pulses are proportional to the phase error between f₁ ' and f₂ '. "Up" pulses from "nor" gate G₁ have widths determined by the outputs of flip-flop F₁ at Q₁, which start at the leading edges of pulses f'₁ and end at the leading edges of pulses f'₂. "Down" pulses from "nor" gate G₂ have a widths determined by the outputs of flip-flop F₂ at Q₂, which start at the leading edges of pulses f'₂ and end at the leading edges of pulses f'₁. "Up" pulses represent a positive phase error, and "down" pulses represent a negative phase error. When f₁ ' and f₂ ' do not overlap, the appropriate "up" or "down" signal, depending upon the sense of the error , is turned on continuously in order to decrease the loop response time for large errors in phase or frequency, and in addition, the magnitude of the current generated by the current pump is increased by gain control transistor T₁. In the normal condition when pulses f₁ ' and f₂ ' overlap, transistor T₁ is normally-conductive, shorting out resistor R₄, and the magnitude of the output current I₀ of current pump 12 is: ##EQU1## In this normal condition, Q₃ and Q₄ are both low and there is no output signal from "non-overlap" gate G₃. However, when pulses f₁ ' and f₂ ' do not overlap, there is an output from flip-flop F₃ or flip-flop F₄ causing an output from "non-overlap" gate G₃, which is inverted by an inverter 28 and renders transistor T₁ cut off so that resistor R₄ is placed in series with resistors R₂ and R₃. The current pump then has a maximum output current given by the formula: ##EQU2## In other words, the output current I₀ increases.

The current pulses from the junction between the transistors T₃ and T₄ in the variable-gain current pump are applied to the variable-bandwidth filter 14 to generate the frequency-control voltage V₀ applied to input 30 of the voltage-controlled oscillator 24. In the normal condition when pulses f₁ ' and f₂ ' overlap, Q₃ and Q₄ are both low, there is no output signal from "non-overlap" gate G₃, transistor T₅ is cut off and resistor R₅ is in series with resistor R₄ and capacitor C₁ in the filter circuit. However, when pulses f₁ ' and f₂ ' do not overlap, there is an output from "non-overlap" gate G₃ which is coupled over path 32 and resistor R₆ to make transistor T₅ conductive. The collector-emitter path of this conducting transistor acts as a short circuit across filter resistor R₅ and with this resistor short-circuited, the filter has a maximum bandwidth. The maximum bandwidth is needed to effect a rapid change in control voltage V₀ and correction of oscillator frequency, and the normal narrower bandwidth is provided when synchronization is achieved to minimize the effects of spurious pulse disturbances in the feedback loop.

The operation of the phase locked loop of FIG. 1 is illustrated by the phase characteristic shown in FIG. 2 and the frequency characteristic shown in FIG. 3. When the input pulse wave f₁ ' and the oscillator pulse wave f₂ ' are exactly equal in phase and frequency, the pulse width of the frequency correction current pulse applied to the variable bandwidth filter 14 is zero. This condition is represented by the origins 0 in FIGS. 2 and 3. If the phases of the pulse waves differ slightly with the pulses overlapping, the pulse width of the correction current pulse is increased and the current applied to filter 14 and stored as a charge or capacitor C₁ produces a control voltage V₀ which has a positive value proportional to the phase difference, as represented by the sloping line in the FIG. 2 phase characteristic between the limits labeled 10%. The range 10% applies where the pulse widths are 10% of the periods of the pulse waves. If the pulse waves differ in phase by more than 10% so that the pulses do not overlap, the "non-overlap" condition is detected by the pulse comparison circuit 10, with the result that the variable-gain current pump 12 produces a correction current I₀ equal to I_(max) or -I_(max) continuously until such time as the phases of the pulse waves are close enough so that the pulses overlap. FIG. 3 shows that whenever the frequencies of the pulse waves are different, the correction current I₀ applied to the filter 14 is always I_(max) or -I_(max) because, when the frequencies are different the pulses do not overlap, except during a very small percentage of the time.

To summarize, when the input pulses overlap, frequency correction current pulses whose widths are proportional to the phase difference are supplied to the variable bandwidth filter 14. This current is integrated by filter 14 to produce a voltage V₀ which is supplied to the oscillator 24. When the input pulses do not overlap, a maximum plus or minus frequency correction current is applied continuously to the filter.

The operation of the pulse comparison circuit 10 will be described with references to waveforms shown in FIGS. 4 and 5. FIG. 4 shows the condition in which the input pulse wave f₁ ' and the oscillator pulse wave f₂ ' are exactly equal in phase (and frequency). Flip-flops F₁ and F₂ both get set and produce outputs Q₁ and Q₂, but the flip-flops are both immediately reset via "nand" gate 26. Therefore the outputs Q₁ and Q₂ are mere minimum-duration spikes passed by both "or" gates G₁ and G₂ to the current pump 12 where they have cancelling effects so that the correction current I₀ is zero.

FIG. 5 illustrates the condition where input pulse wave f₁ ' has a leading phase relative to oscillator pulse wave f₂ ' and the phase difference is great enough so that the pulses do not overlap. Flip-flop F₁ is set by the leading edge of pulse f₁ ' and it stays set producing a Q₁ pulse until flip-flop F₁ is reset through gate 26 when flip-flop F₂ is set by pulse f₂ '. The leading edge of pulse f₁ ' also resets flip-flop F₃ and it remains reset with Q₃ low until the trailing edge of pulse f₁ ' occurs and the Q₁ output of flip-flop F₁ sets flip-flop F₃ and makes Q₃ high. Flip-flop F₃ remains set with Q₃ high until the flip-flop is reset by the next pulse f₁ '. One or the other or both of pulses Q₁ and Q₃ are always present to provide a continuous "up" signal at the output of "or" gate G₁. The "up" signal turns on current pump 12 and applies a correction current to filter 14 from which a correction voltage V₀ is applied to voltage-controlled oscillator 24.

While the current pump 12 is turned on by the "up" signal, flip-flop F₃ is set and providing an output Q₃ in the long intervals between pulses f₁ ' through the "non-overlap" gate G₃. This "non-overlap" signal acts through transistor T₁ to increase the amplitude of the current pulse, producing a faster than normal frequency correction. The "non-overlap" signal also acts through transistor T₅ to make loop filter 32 have its maximum bandwidth. The maximum "up" current signal generated by current pump 12 and the maximum bandwidth in filter 14 cooperate to cause the phase and the frequency of the oscillator to be very rapidly changed into phase and frequency lock with the input signal f₁. When oscillator pulse wave f₂ ' leads input pulse wave, f₁ ', a similar but opposite correction of the oscillator frequency is made as the result of the generation of a "down" signal. 

What is claimed is:
 1. A phase locked loop, comprisinga voltage-controlled oscillator, a phase and frequency detector, a first pulse shaper coupling an input signal wave to a first input of said phase and frequency detector, a second pulse shaper coupling an output of said voltage-controlled oscillator to a second input of said phase and frequency detector, said phase and frequency detector including: a pulse comparison circuit operative when pulses from the pulse shapers overlap to produce "up" signal pulses having widths proportional to the phase difference when the pulses from the first pulse shaper lead, and to produce "down" signal pulses having widths proportional to the phase difference when the pulses from the second pulse shaper lead, and producing a "non-overlap" signal when the pulses of waves from said first and second pulse shapers do not ovelap, a variable-gain current pump means responsive to said "up" and "down" signals to produce an output signal varying in amplitude and polarity with the amount and polarity of the phase difference between the pulse waves from said first and second pulse shapers when the pulses overlap, means to apply said "non-overlap" signal to said current pump to increase the gain thereof to a fixed maximum value, and a loop filter coupling the output of said variable-gain current pump to the voltage control input of said voltage-controlled oscillator.
 2. The combination as defined in claim 1 wherein said loop filter is a variable-bandwidth loop filter.
 3. The combination as defined in claim 2 and, in addition, means to apply said "non-overlap" signal to said filter to increase the bandwidth thereof to a fixed maximum value.
 4. The combination as defined in claim 1 wherein said pulse comparison circuit comprisesfirst and second flip-flops each having a leading edge trigger input, a set output and a reset input, a gate coupling the set outputs of said first and second flip-flops to the reset inputs of the flip-flops so that the flip-flops cannot both remain set, third and fourth flip-flops having set inputs coupled to set outputs of respective first and second flip-flops and having reset inputs and set outputs, means coupling the output of said first pulse shaper to the trigger input of said first flip-flop and the reset input of said third flip-flop, means coupling the output of said voltage-controlled oscillator through said second pulse shaper to the trigger input of said second flip-flop and the reset input of said fourth flip-flop, first gate means responsive to output of said first and third flip-flops to generate said "up" signal pulses, second gate means responsive to outputs of said second and fourth flip-flops to generate said "down" signal pulses, and third gate means responsive to outputs of said third and fourth flip-flops to generate said "non-overlap" signal when pulses of first and second pulse waves do not overlap. 